Abstract
Abstract Modern world is running towards the miniaturized embedded applications so that many achievements are done to make the world to be smarter and one of that approach is that reduction in transceiver design. Transceiver is the device which can works in both ways that is the same module is used as receiver as well as transmitter. The output frequency of the transceiver should vary as per the input signal and the output signal has to handle efficient communication with less noise built in. To meet this requirement, frequency synthesizers and phase locked loops are employed. The proposed programmable frequency dividers are designed in such a way that it achieves the 50% duty cycle. Down counters are also designed and simulated using VERILOG-HDL and implemented by XILINX–ISE. From the results it shows that the proposed design is better in resolving the criteria of achieving the 50%duty cycle.
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