Design of Low-Power and High-Frequency PLL Using Programmable Frequency Divider for Wireless Communication

Abstract

In this paper, a phase-locked loop (PLL) design using programmable frequency divider (FD) is implemented for low-power and high-speed wireless communication. The programmable FD of the PLL is designed with the use of extended true-single-phase-clock (E-TSPC) and the 4-1 multiplexer is designed with gate diffusion input (GDI). Optimized designs are used to minimize the power consumption of the PLL. The SPICE results illustrate that the PLL with GDI circuit consumed less power and delay of the order of 13.5 µW, 2.862 ns, respectively.