Wire congestion aware high level synthesis flow with source code compiler

Abstract

High level synthesis (HLS) is a source-code-driven Register Transfer Level (RTL) design tool, and the performance of a generated RTL is limited by the description of an input code. In order to break through such kind of limitation and to get a further optimized RTL, the optimization of an input source code is indispensable. Routing congestion is one of such problems we need to consider the refinement of an input source code. Routing congestion is, in general, difficult to resolve in HLS due to the lack of physical information. The conventional design flow incorporates logic synthesis and physical synthesis into HLS in order to estimate wire congestion and to feedback the estimation result to the code modification. In this paper, we propose a HLS flow that performs the code improvements by detecting congested parts without using the information from logic and physical synthesis, and the code re-generation using the source code compiler.