Formal Verification of Pipelined Synthesized Designs by Exploiting Intermediary Rtls

Abstract

We propose a formal methodology based on higher-order logic theorem proving for completely automated verification of Register Transfer Level (RTL) designs with pipelined iterative control constructs. We will show that the shortest path in verification of a pipelined design is often not a direct comparison and equivalence checking between the design and its behaviour specification, but through an intermediary design at the same level of abstraction. Viability of automating the entire verification process is a result of: (1) a two-step verification approach that relies on transforming the design into an equivalent non-pipelined RTL to serve as an intermediary between the design and its specification; and (2) identification of three correctness conditions for RTL designs with pipelined control flow, that allow for a concise proof decomposition based on the control and data properties of this class of designs. We use the theorem proving environment PVS (Prototype Verification System) [1], integrated with a synthesis tool, for conducting the verification task. This technique is implemented and integrated in a formal verification tool employed for verifying the correctness of RTL designs generated by a High-Level Synthesis (HLS) system. The technique has been successfully applied for verification of several benchmarks with different Data Introduction Intervals (DII) and clock frequencies.