Wire Bonding Looping Solutions for Advanced High Pin Count Devices

Abstract

The growth of semiconductor industry is driven by more functionality, lower cost and smaller packages. With the proliferation of Cu wire bonding, wire bonding remains the lowest cost interconnect solution for most applications. The higher mechanical strength of Cu wire enables higher loop profiles and longer wire spans which in turn enable high density devices (>2000 I/Os) to be wire bonded. Programming these high density devices can be time consuming. Good looping performance for such packages is needed to ensure high production yield. This paper presents new solutions to improve the design cycle, productivity and yield. Offline 3D Loop Design software is developed to provide wire bond loop profile design during the package design phase. This tool enables 3D wire clearance checks and electrical performance simulations to optimize pad and substrate layout, and enables generation of a wire bond program with optimized loop design. Extensive FEA modeling is performed to understand the factors that affect looping formation and aid the design of looping motion to produce the desired wire bond loops. Looping Parameter Models are developed and implemented on the wire bonder to produce actual loop profiles matching the desired loop programmed in the offline Loop Design software. A wire bonding looping performance map is generated for a large range of loop profiles with a loop height range from 75um to 500um, and wire lengths from 0.5mm to 5mm. The looping performance map includes metrics such as actual vs. desired loop height difference, loop height variations, and loop sway at different locations along the wire span. This performance map is used to improve the loop design and loop clearance check. Factors that influence the wire bond looping performance are also discussed.