Abstract
The rising integration level of mixed-signal integrated circuits raises new issues for designers. Substrate generated by the switching part has a detrimental impact on the performance of the analog/RF parts. This contribution introduces simulation and experimental characterization of so-called digital substrate noise on a 0.13-μm SOI CMOS process with high resistivity (HR) substrate. To the authors knowledge, it is the first time that that it is addressed in SOI technology at circuit level.
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