Abstract
This paper presents the design of a D-band frequency quadrupler (FQ) based on two cascaded frequency doublers. Each doubler relies on the bootstrapped Gilbert cell (GC) mixers. The FQ is developed with a standard 130-nm SiGe BiCMOS process. It consists of fully integrated input and output baluns, frequency doublers, and matching networks. The design of the FQ was optimized via single-ended matching networks to reduce the chip area and increase bandwidth. The results based on the EM-simulation of FQ with the assistance of the hicum model for the transistor, demonstrate a peak conversion gain and output power of 25 dB and 5 dBm, respectively at 130 GHz. The FQ shows a 3-dB bandwidth higher than 84 GHz with an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> harmonic rejection of at least 16 dBc. The FQ can be exploited in various systems design for different D-band applications. The future work includes measurement of the FQ.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
