Wet etching of vias for wafer level packaging of GaAs based image sensor

Abstract

GaAs based image sensor has many advantages over its Si counterparts such as the ability to detect dim light and high sensitivity for higher saturated electron velocity and higher electron mobility. But little work has been reported on the packaging of GaAs image sensor particularly at wafer level. Since the full processed GaAs image sensor wafer is sensitive to high temperature or any plasma processes, it is essential to find out a proper way to form the interconnect for low temperature wafer level packaging of GaAs image sensor. In this work, GaAs wet etching is used to etch grooves from the backside of the device wafer to avoid high temperature and plasma etch processes. The challenge lies in that it is hard to control the etch profiles because of nonuniform etch rate on different crystal faces. Three different kinds of etching solution i.e. (A) 1H2SO4 + 8H2O2 + 1H2O, (B) 9H3PO4 + 1H2O2 + 20H2O, (C) 1K2Cr2O7 + 1HBr + 4CH3COOH are tested to etch useful structures at room temperature with photo resist mask. The results show that solution A has the greatest etching rate with crystallographic etch profiles, solution B has an reasonable etching rate around 15μm/h with very smooth etch surfaces and also crystallographic etch profiles, solution C has the slowest etching rate with smooth etch surfaces and isotropic etch profiles. And finally dovetail grooves suitable for interconnection that perpendicular to direction is reached by solution B with very smooth surfaces.