Abstract
This paper presents a Low Noise Amplifier (LNA) modeled in 65 nm CMOS technology for wideband (110-135) GHz systems. LNA comprises of four stages cascode with L-type matching networks used for input and interstage matching and T-Shape matching networks used at output side. The first stage is designed to improve the noise and input matching and subsequent stages for gain performance. The LNA achieves a flat gain response over a wide bandwidth. The amplifier design is modeled and simulated in Advanced Design System (ADS). The LNA achieves a high gain of 29.11 dB at 124 GHz, Noise Figure (NF) less than 5.2 dB and 3 dB bandwidth of 20 GHz. The S 11 is -19.91 dB at 128 GHz. The LNA dissipates power of 20 mW with 1.8 V supply voltage.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
