Abstract
Emerging non-volatile memory (NVM) technologies are promising alternatives to DRAM. However, the write inefficiency associated with NVM brings significant challenges to the last-level cache (LLC) replacement design. LLC replacement policies in the context of DRAM hardly focus on writeback optimization. Based on the observation that writeback to NVM diminishes the performance gained from replacement optimization, we exploit to improve LLC replacement policy with a writeback-aware reuse stack (Warstack). Warstack enhances the default reuse priority in terms of writeback intensity. Incooperating with an accurate writeback intensity predictor (WBIP), Warstack dynamically ranks the reuse priority and retains high write-intensive blocks to mitigate the write traffic. Evaluations with memory-intensive multi-programmed programs from SPEC CPU2006 show that Warstack improves performance and energy efficiency by about 12% and 15% on average.
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