Composing lifetime enhancing techniques for non-volatile main memories

Abstract

Emerging byte-addressable non-volatile memory (NVM) technologies, such as PCM and ReRAM, offer significant gains in terms of density and power consumption over their volatile counterparts. Their write endurance is, however, orders of magnitude lower than DRAM, potentially causing devices to fail in seconds. Therefore, to use NVM as DRAM replacement, writes must be managed carefully. In this paper, we study the endurance problem for NVM main memories with realistic server workloads. We explore three existing techniques to extend NVM lifetime: last-level cache replacement policies, compression, and NVM wear-leveling. The first two approaches increase lifetime by reducing the write traffic from the cache to the main memory. Wear-leveling spreads writes and reduces hotspots responsible for fast failures. Even though custom replacement policies and compression are common in DRAM caches inside NAND flash devices, we find that they provide insufficient lifetime gains for NVM main memories with realistic server workloads. Caching writes is effective, but adapting the replacement policy only provides modest write reductions by 10%, while compression schemes must quadruple the cache capacity to achieve reductions of 20%. In both cases, the lifetime increases by an order of magnitude, which, for example, translates in an improvement from 12 days to 6 months for PCM. In contrast, wear-leveling algorithms can increase overall lifetime by at least two orders of magnitude, for instance, from 12 days to 15 years for PCM. These results indicate that wear-leveling techniques are more promising to ensure that NVM technologies are feasible to use as DRAM replacement.