Warpage measurement and simulation of flip-chip PBGA package under thermal loading

Abstract

The aim of this study is to measure and simulate warpage of flip-chip PBGA packages under thermal loading (from room temperature to 260degC). In the experiments, a full-field shadow moire is used for measuring real-time out-of-plane deformations (warpages) on the substrate surfaces of the flip-chip packages under heating and cooling conditions. The elastic moduli (Es) and coefficients of thermal expansion (CTEs) for organic substrates are measured in terms of temperatures by dynamic mechanical analyzer (DMA) and strain gage (instead of conventional thermal mechanical analyzer, TMA), respectively. A finite element method (FEM) and Suhir's die-assembly theory cooperating with these measured material data are employed to analyze the thermal-induced deformations of the packages, in order to understand the insight of mechanics. The strain gage data not only successfully provide the CTEs of the substrates, but indicate there is nearly no bending strain occurring under thermal loading. The full-field warpages on the substrate surface of the packages from shadow moire are documented under the temperature loading. It is also found that there are different zero-warpage temperatures (which results in variation of warpages at room temperature) for the four test packages during thermal loading, but with similar warpage rate (the slope of warpage with respect to temperature). It might be due to the creep of the underfill and solder bumps in the packages at the solder reflow temperature. Regardless of the zero-warpage temperature, the warpage of the packages can be simulated or predicted by the FEM and Suhir's theory. Key material properties (Es and CTEs for the substrate and underfill) to affecting the maximum warpage of the package are thoroughly studied. It is found that among those material properties the low E of the underfill can significantly reduce the maximum warpage, while its CTE is much more insensitive to warpage.