Mechanical Behavior of Flip Chip Packages under Thermal Loading

Abstract

Concern on stresses in solder bumps/underfill and warpage of flip chip BGA packages increases recently because reliability of flip chip packages relates directly to the corresponding stresses and warpage. In addition, when die size increases, the problem becomes more annoying. This problem is mainly due to mismatch in the coefficient of thermal expansion (CTE) and Young's modulus for materials made of substrate, silicon chip, underfill, and solder joints. In this paper, CTE for BT substrates were measured using electronic speckle pattern interferometry (ESPI) in different manufacturing stages to understand the effect of via drilling, Cu plating and patterning, and solder mask coating. The effect due to solder mask coating on CTE change was found to the most significant. Further, the CTE of BT substrates used in wire bond BGA packages and flip chip BGA packages varied significantly due to use of different core materials and different thickness of solder mask. On warpage measurement, 40 /spl times/ 40 mm FC BGA with die size equal to 10 /spl times/ 10, 20 /spl times/ 20, and 26 /spl times/ 26 mm and thickness equal to 730 and 400 /spl mu/m were employed and the measurement was performed from room temperature up to 225/spl deg/C. The phase-shifted shadow moire technique was adopted for this warpage measurement. 2D and 3D finite element models were also constructed to analyze the warpage and stresses of these FC BGA packages. It was found that with accurate CTE data of the substrate as the input the predicted warpage was in excellent agreement with the experimental data, which made it possible to perform meaningful parametric analyses and optimal design of large-sized FC BGA packages.