Warpage Behavior on Silicon Semiconductor Device: The Impact of Thick Copper Metallization

Michele Calabretta,Alessandro Sitta,Salvatore Massimo Oliveri,Gaetano Sequenzia

doi:10.3390/app11115140

Michele Calabretta, Alessandro Sitta + Show 2 more

Open Access

https://doi.org/10.3390/app11115140

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Abstract

Electrochemical deposited (ECD) thick film copper on silicon substrate is one of the most challenging technological brick for semiconductor industry representing a relevant improvement from the state of art because of its excellent electrical and thermal conductivity compared with traditional materials, such as aluminum. The main technological factor that makes challenging the industrial implementation of thick copper layer is the severe wafer warpage induced by Cu annealing process, which negatively impacts the wafer manufacturability. The aim of presented work is the understanding of warpage variation during annealing process of ECD thick (20 μm) copper layer. Warpage is experimentally characterized at different temperature by means of Phase-Shift Moiré principle, according to different annealing profiles. Physical analysis is employed to correlated the macroscopic warpage behavior with microstructure modification. A linear Finite Element Model (FEM) is developed to predict the geometrically stress-curvature relation, comparing results with analytical models.

Highlights

Formation of copper thick film on silicon substrate is desirable in the semiconductor industry because of its excellent electrical and thermal conductivity [1,2]
The measurement outputs considered for the presented work are the warpage maps shown in Figure 4, captured at different time of temperature profile, during both the heating and cooling phases
The warpage trend in temperature during the heating phase shows a change in slope that occurs at 150 ◦C, at which warpage reaches its maximum

Summary

Introduction

Formation of copper thick film on silicon substrate is desirable in the semiconductor industry because of its excellent electrical and thermal conductivity [1,2]. Stabilizing metal grain size, annealing permits to avoid electromigration issues in interconnect reliability, e.g., during reliability application related test [14,15,16,17] or passive thermal cycles [18,19] It seems to miss in literature a detailed experimental warpage analysis for thick Cu layer: available data refer about maximum 5 μm thick Cu metal [3,20]. The final target of this paper is to correlate the warpage behavior of silicon devices with thick (20 μm) ECD copper film with physical modification induced by thermal treatment, such as annealing, and to find out a reliable numerical model to predict warpage. An analysis on micro-structure evolution due temperature evolution in the range between 150 and 250 °C permits to understand if it is possible optimize manufacturing process to reduce the residual warpage

Sample and Test Description

Results

Physical Analysis

Finite Element Model for Warpage Calculation

Conclusions