Abstract

AbstractElectrochemical deposited (ECD) thick film copper on silicon substrate is one of the most challenging technological brick for semiconductor industry representing a relevant improvement from the state of art because of its excellent electrical and thermal conductivity compared with traditional compound such as aluminum. The main technological factor that makes challenging the industrial implementation of thick copper layer is the severe wafer warpage induced by Cu annealing process, which negatively impacts the wafer manufacturability. The aim of presented work is the understanding of warpage variation during annealing process of ECD thick (~20 µm) copper layer. Warpage has been experimental characterized at different temperature by means of Phase-Shift Moiré principle, according to different annealing profiles. A linear Finite Element Model (FEM) has been developed to predict the geometrically stress-curvature relation, comparing results with analytical models.

Highlights

  • Thick film copper on silicon substrate is one of the major challenges in the semiconductor industry because of its excellent electrical and thermal conductivity

  • The integration of Cu into integrated circuit (IC) is still a technical challenge due to the severe wafer warpage induced by Cu annealing, which affects the accuracy of the subsequent manufacturing processes, such as the wafer handle and the adsorption of vacuum suction cup, having a negative impact on device reliability

  • Stabilizing metal grain size, annealing permits to avoid electromigration issues in interconnect reliability, e.g. during reliability application-related test [3, 4]. It seems to miss in literature a detailed experimental warpage analysis for thick Cu layer: available data refer about maximum 5 μm thick Cu metal

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Summary

Introduction

Thick film copper on silicon substrate is one of the major challenges in the semiconductor industry because of its excellent electrical and thermal conductivity. Stabilizing metal grain size, annealing permits to avoid electromigration issues in interconnect reliability, e.g. during reliability application-related test [3, 4]. It seems to miss in literature a detailed experimental warpage analysis for thick Cu layer: available data refer about maximum 5 μm thick Cu metal. For what concerns analytical models, Stoney equation [5] have been commonly used as reference This formula has been developed for “membranelike” geometries made by two materials, such as the system made by semiconductor wafer and ECD metal, in which one layer (in our case, ECD Cu) is much thinner than other. Numerical outcomes have been compared with the results of Stoney and Timoshenko equations

Sample and Test Description
Warpage Measurements
Finite Element Model
Conclusions
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