Wafer-Level hermetic packaging for bio-medical applications

Abstract

Introduction Packaging of medical implants has been always a challenging topic due to the strong requirements in term of sizes, biocompatibility and safety [1, 2]. This is often required for placing an implant at a specific location of the body, without disturbing the surrounding tissues, and aiming at avoiding discomfort for the patient. The implants should be packaged in order to have a hermetic closed shield around the device, protecting the human body from diffusion of materials from inside the package into the body [3, 4]. Moreover, in order to ensure the functionality of the implanted device, the package should also protect the device from any insertion of body fluids into the implant, especially for active electronics. An implantable device could consist of several subdevices connected each other and integrated in a single package. These sub-devices could be one or more CMOS chips, a battery, a sensor, etc. They need to be electrically connected with each other and if required be accessible through the guest body by dedicated electrodes. We present here a process flow (Figure 1) aiming at encapsulating single dies as commodity Integrated Circuits (IC). The encapsulation consists of a stack of layers, to prevent diffusion of metal contaminant, prior to final encapsulation in a bio-compatible package. The reported process relies on classical CMOS and 3D wafer-level packaging processes. The test devices for encapsulation consist in test silicon chips with Cu metal structures designed to be characterized in a standard daisy chain configuration. A double diffusion barrier is created on the top side of the chip to avoid Cu diffusion. The first barrier consists on a thick layer of Silicon nitride which offers superior performance with respect to Cu diffusion in the immediate vicinity of the interconnect layers. After this step the wafer is processed with Dicing-BeforeGrinding (DBG) technique. A thick silicon oxide is deposited on the sidewalls of the pre-grooved wafers to protect the edge of the IC dies, prior to thinning the wafer down to ~80μm. The sharp edges from the backside of IC dies are then rounded and a 3μm thick oxide deposited at low temperature is deposited to complete the encapsulation. Finally, the test chips are de-bonded and cleaned. The functionality of the encapsulation process as diffusion barrier is tested by various experiments as cell culture test and leaching test followed by TXRF analysis of the elution. After the hermetic encapsulation of single dies, the next step would be the assembly of the final device. The various sub-devices will be connected through a bio-compatible inter-die metallization (e.g. gold, platinum or other) that will have access to the die’s active site by electrodes also them metalized with biocompatible materials (Figure 2a). The total system will be then further encapsulated by using embedding technique where a flexible and biocompatible material [6] will be used to provide the dies a sufficient mechanical support (Figure 2b).