Wafer-to-Wafer Hybrid Bonding Development by Advanced Finite Element Modeling for 3-D IC Packages

Abstract

This article focuses on the 3-D modeling methodology development of the wafer-to-wafer hybrid bonding (W2W-HB) annealing process. With its successful application in a 2-stack wafer-to-wafer bonding, the Cu-to-Cu bonding area is derived and compared for various design and process conditions, such as dishing value, annealing temperature, and dwell duration, through-silicon via (TSV) depth, and TSV/Cu pad pitch. Cu protrusion during the annealing process induces peeling stresses on both Cu and dielectric bonding interfaces. The resulting debonding risk for both Cu and dielectric bonding is assessed by comparing the peak interfacial peeling stresses for various scenarios. The impact of wafer designs with or without TSV has also been studied. The key advantage of this numerical study is to help establish design and process guidelines to shorten the W2W-HB process development cycle and achieve robust bonding integrity. The outcome of this work has been successfully implemented in the actual process.