Wafer level reliability assessment of stress-induced voiding

Abstract

As device technology advances toward submicron geometry, the linewidth of VLSI metallization interconnects continues to scale down and stress-induced migration becomes an increasingly important issue. Wafer level stress-induced migration testing of metallization was introduced as a technique for obtaining greater levels of quality assurance with a shorter feedback time at an affordable cost. Slit-like voids are typically formed causing catastrophic open-circuit failures. The results indicate that metal linewidths of around 1 mu m and below are more susceptible to stress-induced voiding. Multilevel submicron technology requires either a new metal or a barrier metal system such as TiN under metal-1. Furthermore, the use of a well designed look-ahead test vehicle has proven its effectiveness in assessing potential metallization reliability issues early in the technology development phase. >