Abstract
A new wafer-level 3D system integration process that relies on a novel multi-level 3D redistribution layer technology (3D-RDL) to interconnect chips together as well as to the substrate was developed. The 3D-RDL technology is based on a single electroplating step that allows routing high density, auto-adaptive vertical copper interconnects (20 μm Line/Space “L/S”) at the edge of known-good dies as well as redistribution layer on top of the die and the substrate. Furthermore, this technology enables 3D interconnection of stacked dies using a single 3D-RDL layer. Additionally, high performance 3D inductive devices with small form factor can be integrated above-IC or above-substrate using the same 3D-RDL processing steps. These capabilities allow miniaturization and performance enhancement and make the technology ideal for various applications requiring functional heterogeneous system integration on a small footprint, such as systems for mobile and Internet-of-Things (IoT) applications, MEMS and Sensors.
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