Abstract
This chapter will examine high-voltage direct current (HVDC) system responses to DC and AC faults from a theoretical perspective. The analysis will consider the HVDC topology two-level voltage source converter (VSC). The test system is shown in Fig. 4.1, where the location of faults is also illustrated. The investigation is concerned with system responses for faults located at the converter DC or AC bus, which is the worst-case fault location, and it is representative for faults further away from the converter. It is presumed that faults will not happen closer to the converter, because this area is located in the valve hall and faults are unlikely. If faults happen closer to the converter, then the fault current will be too fast and strong for the normal protection methods, and insulated gate bipolar transistors (IGBTs) will be tripped by the internal switch-level protection.
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