Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access

Abstract

This paper investigates the impact of voltage scaling on energy and performance of STT-MRAM arrays under write access, which is well known to be energy critical. Simple analytical models of energy and delay are introduced to gain an insight into the energy-performance tradeoff at low voltages, and minimum-energy operation. The minimum-energy point is found to lie at voltages that are substantially higher than CMOS logic and memories. The impact of voltage scaling on the area-energy-performance tradeoff on most representative STT-MRAM bitcells is investigated and justified through the proposed models. Interestingly, bitcell area optimization is shown to enable 25%–40% energy savings compared to minimum-sized bitcells, when operating at low voltages. Results show that the write energy reduction achieved through voltage scaling strongly depends on the adopted bitcell, and was found to be up to 20%–30% in a 65-nm and 28-nm array. Voltage scaling is expected to become mainstream in STT-MRAM design, as promising approach to mitigate the well-known issue of large write energy consumption.