Voltage-limitation-free analytical single-electron transistor model incorporating the effects of spin-degenerate discrete energy states

Abstract

A physically based analytical single-electron transistor (SET) model is proposed. This model virtually shows no voltage limitation in the scope of the orthodox theory, which makes it particularly suitable for hybrid simulation where the SET is biased by a current source. The model is verified against Monte Carlo simulation with excellent agreement and compared to existing models. It is found that our model is valid and accurate whatever the drain voltage and faster than reported models on the whole. A way to integrate into the model the effects of spin-degenerate quantum energy level discreteness, in the case of a silicon-based SET, is also introduced and observed quantum mechanical effects, such as negative differential conductance, are discussed.