Abstract
A novel quasi-analytical model for Single Electron Transistors (SETs) is proposed and validated for both symmetric and asymmetric devices by comparison with Monte Carlo simulations in terms of both drain current and conductances. The proposed method is based on the separate modelling of the tunnelling and thermal components of the drain current, and verified over two decades of temperature. For the first time, accurate modelling of SET (trans) conductance is demonstrated. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in static and dynamic regimes and appears attractive for hybrid (SET-CMOS) circuit co-simulation.
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