Abstract
The potential damaging effects of high inrush currents occurring after power quality disturbances on switch-mode dc power supplies (SMPS’) have been reported, but have not been studied in detail. This paper presents a new analytical model for the accurate representation and calculation of inrush currents of low-power SMPS devices. This model is verified against previously developed circuit-based simulation model and compared with the only other analytical model available in existing literature. The developed analytical model is also used to investigate device protection co-ordination, in order to demonstrate two important effects of high-inrush current: nuisance tripping of protection and damage of internal SMPS components.
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