Void-Free Copper Electrodeposition in Full Wafer Thickness through-Silicon Vias with 10:1 Aspect Ratios

Abstract

The incorporation of copper-filled, mesoscale through-silicon-vias (TSVs) as a three-dimensional integration technique allows for increased input/output per unit volume compared to wire bonded microelectronic devices. Mesoscale TSVs that span the full thickness of a silicon wafer allow for preservation of a large radius of curvature during multi-layer device fabrication and for conservation of mass in the device, which is often a requirement in MEMS applications. The damascene process is commonly implemented for Cu electrodeposition in high aspect ratio features and typically involves a three-additive system in a CuSO4-H2SO4 electrolyte. However, a single-additive system has recently been shown capable of achieving bottom-up superfilling in features with higher aspect ratios than those commonly used in damascene interconnects.[i] This resistive electrodeposition system utilizes CuSO4, methane sulfonic acid (MSA), chloride, and a poloxamine suppressor additive. Cyclic voltammetry (CV) can be used to characterize the plating solution and identify a potential range that exhibits hysteresis in the voltage-current relationship that is caused by suppressor disruption at the cathode surface during electrodeposition. This hysteretic region serves as an operating window where void-free Cu filling of high aspect ratio features may be achieved. Using this chemistry, potentiostatic and galvanostatic plating conditions for void-free filling were developed for 100 μm diameter vias that are 600 μm deep, a 6:1 aspect ratio.[ii],[iii] Cu electrodeposition in TSVs with a higher aspect ratio of 10:1 is currently under investigation. These TSVs have a 62.5 μm diameter etched into a 625 μm thick silicon-on-insulator (SOI) wafer. Conditions that produce void free, bottom-up filling for 100 μm diameter TSVs have not directly translated to fill 62.5 μm diameter TSVs. In this work, the poloxamine suppressor concentration, current, potential, and sample rotation rate were varied to analyze their effect on the fill profile in these 62.5 μm diameter TSVs. Fill profiles were analyzed after mechanically cross-sectioning and optically imaging the samples. Cu fill profiles were also obtained through X-ray computed tomography (CT) scans. This work details the experimental approach associated with determining galvanostatic and potentiostatic plating conditions for 62.5 μm diameter TSVs and presents the resultant fill profiles of Cu in these vias. Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. [i]. Moffat, T. P., and D. Josell. "Extreme bottom-up superfilling of through-silicon-vias by damascene processing: suppressor disruption, positive feedback and turing patterns." Journal of the Electrochemical Society 159.4 (2012): D208-D216. [ii]. Menk, L. A. et. al. “Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology.” Journal of the Electrochemical Society 166.1 (2019): D3066-D3071. [iii]. Menk, L. A. et. al. “Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs” Journal of the Electrochemical Society 166.1 (2019).