VLSI processor array IPS cells

Abstract

Various types of linear systolic and VLSI processor array designs are analyzed in this paper. The aim is to analyze the processor operation in these designs and derive a description of the requirements for a general IPS cell. Three types of standard IPS cells are determined according to the number of data streams or the use of a resident memory value. Also another criterion is the location of the output data stream or the storage of the update results. Four types of switched IPS cells are determined according to the memory or I/O alternation. The criteria of choosing three or two data streams (possible resident data stream) produces differences in these cells. Memory alternation can be determined whether the switched resident values are only input values or the update results are stored. The I/O alternation means that the output data stream is divided into two paths and the update result is output in one path on even time moments and in another on odd time moments. The most complex is the cell with both the memory and I/O alternation. Four types of double IPS cells are determined whether there are resident memory values or not, and whether one or two output data streams flow in the array. Each of these solutions achieves twicefold speedup and efficiency according to the conventional BLA and ULA solutions. A WARP cell can emulate most of these cells, but in addition it has many properties that diverge from the ‘pure systolic’ design.