Abstract
The VLSI Ethernet controller chips are discussed from a designer's viewpoint. Their method of operation is explained and design tradeoffs are presented with concentration placed on memory response requirements, memory location options relative to the VLSI devices, and the effects of FIFO depth on performance. A "common sense" architecture for an Ethernet node processor with application to many classes of Ethernet nodes is suggested to conclude the paper.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
