Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits

Abstract

ABSTRACT Most of the portable systems, such as cellular communication devices, and laptop computers operate from a limited power supply. Devices like cell phones have long idle times and operate in standby mode when not in use. Consequently, the extension of battery-based operation time is a significant design goal which can be made possible by controlling the leakage current flowing through the CMOS gate. This article reviews the off-state leakage mechanisms like weak inversion leakage, gate induced drain leakage and channel punchthrough current. Various circuit level techniques to reduce standby leakage and their design trade-off are discussed. Based on the surveyed techniques, a designer would be able to select the appropriate leakage optimization technique for a standby mode. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – VLSI (very large scale integration). leakage in CMOS circuits which are depicted in Figure 1[1].