VLSI implementation of image scaling processor

Abstract

This paper focuses on reducing the power, area and the gate counts required to implement an image scaling processor. This image scaling technique consists of a combined filter that incorporates sharpening and clamp filter and a bilinear interpolator. The combined filter acts as a pre filter to reduce the blurring effects in the image. The gate count is reduced by considering a T-model and an inversed T-model convolution kernel which helps in realizing the sharpening spatial filter and the clamp filter. Further, in the combined filter, the two T-models or the inversed T-models are combined thereby the design requires only one-line-buffer memory. In addition to which the resources and the hardware cost of the bilinear interpolator can be efficiently decreased by using the Spurious Power Suppression Technique (SPST) adder in the reconfigurable calculation unit (RCU). This technique has been implemented in SPARTAN 2E - XC2S600E-6FG676 family at the speed of 115 MHZ.