Abstract
This paper is proposed on utilization of the Brent-kung adder (BKA) using Spurious Power Suppression Technique (SPST) that finds application in digital filters and other machine learning algorithm. Design of conventional adder with n stages, adders which are cascaded. The sum and carry outputs of adder cannot be calculated at any stage till the input carry occurs, thus it leads to delay in the process. So to overcome the area and delay, it is a low power high speed Brent kung adder is proposed which is a fast adder. To improve the speed of Spurious Power Suppression Technique (SPST) using Brent-Kung adder, from fast to fastest BKA is used. This paper discusses the 16-bit adder with Spurious Power Suppression Technique (SPST). The results were simulated using Xilinx-Vivado tool. The proposed SPST Brent-Kung Adder have a power consumption of 5448nw and area of 7 cells/area which is less when compared with other SPST adder.
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