VLSI implementation of digit-recurrent CORDIC with constant scaling factor

Abstract

A new high-speed redundant and on-line CORDIC processor with constant scaling factor is presented based on a variant of the original CORDIC algorithm. The new processor has the advantages of high throughput rate, low hardware cost, sample controls and full functionality. The radix-2 signed-digit (SD) redundant arithmetic is used to reduce the carry-propagation delay in the conventional binary adders. The pipelined structure is adopted to increase the throughput rate while the on-line (digit-serial) arithmetic reduces the hardware cost and I/O requirement. Compared to previously proposed methods, the new redundant and on-line CORDIC preserves the constant scaling factor, an important merit of the original CORDIC, and thus does not require any complicated division or variable scaling factor calculation. Furthermore, it can perform both the CORDIC evaluation for angle calculation and the CORDIC application for rotations. VLSI implementation of the processor using Compass 0.6 /spl mu/m standard cell library is also included.