Abstract
In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.
Highlights
Advantages of both MIMO system and Orthogonal Frequency Division Multiplexing (OFDM), i.e., immunity to delay spread as well as huge transmission
The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate
FPGA has been chosen as the target platform because OFDM has large arithmetic processing requirements which can be restricted if implemented in software on a Digital Signal Processor (DSP)
Summary
Advantages of both MIMO system and OFDM, i.e., immunity to delay spread as well as huge transmission. The complexity of MIMO channel estimation is antennas, the spatial dimension can be exploited to improve the performance of the wireless link. The multiple antennas at the transmitter and receiver in a wireless system, where the rich scattering channel can be exploited to create a multiplicity of parallel links over the same radio band to either increase the rate of data transmission through multiplexing or to improve the system reliability through the increased antenna diversity. The objective of this study is to carry out an efficient implementation of the OFDM system (i.e., transmitter and receiver) using “Field Programmable Gate Array (FPGA)” in such a manner that the use of hardware resources can be minimized and system performance is improved.
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