Abstract
An optimization technique for an efficient design of a Multi-Standard Digital Up Converter (DUC) based FIR filter Architecture to minimize area and power consumption. Digital Up Converter will converts low signal sample rate into high signal sample rate. The existing design of DUC has internal shift add logic block which is used to partial product generation but it was complex and consumes more power. This drawback overcomes shift add logic block is replaced into Hybrid Full Adder logic. This Hybrid Full Adder has Gate Diffusion Input (GDI) logic which reduces transistor counts and minimizes addition and multiplication operation compared to shift and add logic. This proposed designed architecture has achieved in reducing the power and area along with the improvement of operating frequency.
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