Abstract
The design of a special-purpose VLSI CMOS processor network for the implementation of the decimation-in-frequency FFT algorithm is described. The design is composed of several pipelined processors. The processors are microcode-controlled for adaptability to other signal processing applications. Calculations are performed in 23-bit floating-point format. The command repertoire for each processor allows the user to perform complex number addition subtraction or multiplication by the use of single commands.
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