VLSI Design of a High Performance Decimation Filter Used for Digital Filtering

Abstract

With the rapid development of computers and communications, more and more chips are required to have small size, low-power and high performance. Digital filter is one of the basic building blocks used for implementation in Very Large Scale Integration (VLSI) of mixed-signal circuits. This paper presents a design of decimation filter used for digital filtering. It consists of Cascode Integrated Comb (CIC) filters, using Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters structure. This architecture provides small area and low power consumption by avoiding the use of multiplication structure. This design presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either ASIC. This has been achieved by porting the netlist of the Simulink system description into the Very high speed integrated circuit Hardware Description Language (VHDL). At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. A comparison of several architectures of this circuit based on different architectures of most popular filter is presented. The comparison includes: supply voltage, power consumption, area and technology. This approach consumes only 2.94 mW of power at a supply voltage of 3V. The core chip size of the filter block without bonding pads is 0.058 mm2 by using the AMS 0.35 µm CMOS technology.