VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

Abstract

The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block $$(8 \times 8)$$ , the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed.