Abstract
Classic Reed-Solomon (RS) codes and binary Bose-Chaudhuri-Hocquenghem (BCH) codes, which can be considered as a special case of RS codes, are utilized for error correction in numerous systems, such as Flash memories, optical communications, wireless communications, magnetic storage, and deep-space probing. Additionally, RS and BCH codes are interleaved/nested to form high-gain coding schemes, including product and product-like codes and the recent generalized integrated interleaved codes, which are among the most promising candidates to address the hyper-speed and excellent-correction-capability requirements posed by next-generation terabit/s digital communications and storage. In recent developments, RS codes are also split/nested/coupled to form locally recoverable erasure codes and minimum storage regenerating codes that substantially improve the efficiency of failure recovery and enable the continued scaling of large-scale distributed storage. In this article, prominent decoder architectures for classic RS/BCH codes are elaborated and the fundamental mathematical reformulations leading to the architectures are explained. Then the challenges and recent advancements on the decoder design of nested RS/BCH codes are highlighted. Erasure-correcting RS decoders for failure recovery are also briefly discussed. The goal of this article is to provide comprehensive understanding of state-of-the-art VLSI architectures for classic RS/BCH codes and introduce the most recent architectures for new coding schemes built by nesting/coupling RS/BCH codes for emerging applications.
Highlights
R EED-SOLOMON (RS) codes [1] and binary BoseChaudhuri-Hocquenghem (BCH) codes [2], [3], which are a special case of RS codes in terms of en/decoding, are among the most broadly-used error-correcting codes since they have efficient en/decoders, good error-correcting capability, and wide range of supported code parameters
This article discusses the VLSI architectures for implementing classic RS/BCH codes as well as new codes built by nesting/coupling RS/BCH codes that are potential key enablers of many next-generation technologies
Extensive discussions have been given to the key equation solver (KES) step for classic RS/BCH decoding
Summary
R EED-SOLOMON (RS) codes [1] and binary BoseChaudhuri-Hocquenghem (BCH) codes [2], [3], which are a special case of RS codes in terms of en/decoding, are among the most broadly-used error-correcting codes since they have efficient en/decoders, good error-correcting capability, and wide range of supported code parameters. ZHANG: VLSI ARCHITECTURES FOR REED–SOLOMON CODES: CLASSIC, NESTED, COUPLED, AND BEYOND three-error-correcting BCH codes have been utilized as component codes to achieve throughput beyond hundreds of Gigabit/s for optical transport networks [9]–[12]. Brief discussions are included for three-error-correcting BCH decoder architectures, which have very short decoding latency and are considered for storage class memories and optical communications. The reviews in parts two and three cover the most recent developments on the decoder architecture design of those new codes built upon nesting/coupling RS/BCH codes for emerging technologies. They point out current state of the art and hopefully serve as the starting point for future research.
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