VLSI architecture of a wireless channel estimator using sequential Monte Carlo methods

Abstract

The regular and repetitive nature of the sequential Monte Carlo (SMC) method makes it very attractive for implementation using parallel and pipelined architectures. This paper develops a VLSI architecture for the hardware implementation of the SMC algorithm using bootstrap filter. A flat fading wireless channel is considered as our framework on which the channel estimator is designed and implemented using the SMC method. The design and verification activities at the algorithm level, architecture level, and the circuit level are reviewed. The proposed architecture is verified with an FPGA implementation.