VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements

Abstract

The code-excited linear predictive (CELP) coder is the most effective technique among various linear predictive coding methods for speech compression. Hence, designing a relatively low-cost and low-power CELP decoder chip for the portable systems and wireless digital communication environment becomes increasingly important. This paper presents the VLSI architecture and chip implementation for the FS1016 CELP decoder with reduced power and memory requirements. A single-chip implementation of the CELP decoder drastically reduces the cost and the size of many CELP vocoder systems. The decoder chip can achieve the following: (1) excellent accuracy results due to the accuracy studies for the finite word length, (2) power savings and high-speed operations owing to the combined advantages of pipeline and concurrent processing structures, (3) table size reducing by applying the memoryless realization for stochastic codebook and partial sums technique and (4) specification satisfying the FS1016 CELP coder. Fabricated with 0.8 μm double-metal CMOS technology, the chip contains approximately 13 000 transistors occupying a 6.1 × 6.2 mm 2 area. It has been tested to be fully functional at IMS XL-60 tester and is the first working FS1016 CELP 4.8 K decoder chip. In particular, the fixed-point accuracy studies for the CELP decoder are also addressed herein.