A programmable application-specific CELP processor with parallel architectures

Abstract

The code excited linear predictive (CELP) coder has been widely used as the most effective technique among various linear predictive coding methods for speech compression. However, it is computationally intensive and general-purpose DSP chips are usually not powerful enough to handle such coding algorithms. The CELP processor architecture and a VLSI implementation are presented. A programmable application-specific single chip design for the CELP algorithm will drastically reduce the cost and achieve real-time performance. The CELP processor is programmable and contains a specific modular design for the codebook searches. On the whole, the chip can process 40 MHz sampled speech data. The FS1016 CELP coder was implemented on this processor, that is we can encode the speech data at 4.8 kbps in real-time using this single chip. Fabricated in 0.8 /spl mu/m double-metal CMOS technology, the chip size is 6.3/spl times/6.1 mm/sup 2/ and is the first chip designed for CELP.