VLSI and Hardware Implementation Using Machine Learning Methods: A Systematic Literature Review

Abstract

Machine learning (ML) tools have been increasingly important in the creation of smart systems in recent years. In several domains, such as autonomous and semi-autonomous vehicles and automobiles, security, healthcare, marketing client profiling, and many other applications, ML technologies have been pushing for a big shift. The necessity for high-performance processing resources is one of the primary challenges for ML techniques. Hardware accelerators have recently been developed to accommodate the processing power required by ML tools. These hardware accelerators were developed using many hardware design approaches such as field-programmable gate arrays (FPGAs), graphics processing units (GPUs), and application-specific integrated circuits (ASICs), to boost computationally expensive operations, according to the literature. These hardware accelerators deliver high-performance hardware while maintaining the requisite precision. A comprehensive literature review is presented in this chapter, which mainly focuses on the designed hardware accelerators for ML algorithms for the past decade. We have studied and analyzed more than 150 different research papers that were published between the years 2011 and 2020 and reported hardware implementations of ML algorithms.