Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy

Abstract

Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were proposed and demonstrated. In all measurements, the tip-sample voltage difference was cancelled during gate–source voltage ( $V_{\text {GS}} $ ) application. Variation in the $V_{\text {GS}} $ -dependent carrier distribution was reasonably determined using both of the proposed techniques.