Vision-Based Metal Oxide Semiconductor Transistor-Level Layout Error Classification Using EfficientNet Model

Abstract

In response to the emerging challenges of providing intelligent dynamic integrated circuit (IC) layout checking, computer vision in IC design and constraint engineering highlights the opportunities of computational intelligence solutions. In this study, vision-based system architecture is integrated with deep transfer learning models to classify metal oxide semiconductor (MOS) transistor cell-level layout error using one-vs-rest (OvR) multilabel classification. Two layout errors, namely missing contact layer and excess structure around the gate, are generated using the developed tool command language (TCL) script that is executed on Synopsys platform. Missing contact layer error is furtherly subcategorized to metal 1 in place and not fully placed, off positioned contact and its combination. Excess structure around the transistor gate is characterized by excess p-type implant (PIMP) and n-type implant (NIMP) with misaligned diffusion (DIFF) and polysilicon (PO) layers. Feature extraction for MOS-level error classification explored on using MobileNetV2 and EfficientNet variants. It was found that EfficientNetB7 best MobileNetV2 and other variants of EfficientNet in predicting IC layout errors based on nine error subcategories. Hamming loss was found to decrease and inference time to increase as the input image size is increased. The deep transfer network EfficientNetB7 has accuracy of 96.889 %, precision of 88.778 %, recall of 97.444 % and F1score of 91.667 in predicting transistor-level layout errors. Overall, the developed approach in predicting MOS transistor cell-level layout error using integrated computer vision and deep learning proved to be accurate and easy to be replicated for further enhancement to provide advanced layout evaluation.