Influence of the gate internal impedance on losses in a power MOS transistor switching at a high frequency in the ZVS mode

Abstract

In order to use a power metal oxide semiconductor (MOS) transistor switching in the zero voltage mode at high frequencies, the output capacitance has to be maximal and the input capacitance minimal. These characteristics are available in the datasheets. Nevertheless, to choose a transistor ideal for such an application, having minimal losses, additional characterizations have to be done in order to complete the datasheets. In particular, it is necessary to make sure that all the cells of the MOS transistor can be opened in a time shortly before the voltage rise time at turn-off, in order to reduce as low as possible the turn-off losses. The present paper points out that the gate to source impedance characterizes the ability of the device to turn-off very quickly and the knowledge of that parameter is useful to choose a MOS transistor having minimal losses in very high frequency zero voltage switching (ZVS) applications.