Virtual signal processors

Abstract

The introduction of SRAM-based field programmable gate arrays (FPGAs) has opened up a new dimension to parallel computing architectures. This paper describes an alternative approach to parallel computing — reconfigurable or virtual parallel processing (VPP). Rather than mapping an application onto a given parallel machine, the WP approach synthesizes the appropriate type and number of processing elements, as well as the interconnection topology, that is optimal for the application. For each application, configuration data is downloaded to the machine that personalizes the hardware for the task at hand. The paper provides a brief description of the authors reconfigurable computer, Archimedes. The benefits of the VPP approach are highlighted by two example applications — the 2-D FFT and a narrow-band digital filter. A novel parallel implementation of a polynomial transform based 2-D transform is described and compared with results for distributed memory parallel machines that have been reported in the literature. The comparison highlights the computational advantage provided by reconfigurable computing. The digital filter implementation employs sigma–delta modulation encoding to reduce the arithmetic workload. The application of this technology to a communications receiver is explained.