Abstract
The potential for via-mid through-silicon vias (TSVs) can be considerable, since their use allows not only a reduction in interconnect length from several mm to several microns, but also a tremendous increase in bandwidth between the stacked chips. The net result is less power consumption, higher performance, increased device density within a given chip footprint, and greater potential to integrate diverse technologies at an overall lower cost. This presentation will cover the manufacturability outlook for via-mid TSVs including equipment, process, and metrology maturity.
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