Predicting the Reliability of Zero-Level TSVs

Abstract

Through Silicon Vias (TSV) are the next generation technology for system in package devices and are similar to plated through holes in a PCB from a reliability behavior perspective. The promised advantages include thinner packages and a greater level of integration between active die. The process is still being optimized and costs must be reduced for widespread adoption. TSV is rarely justified by just miniaturization alone as it is more cost-effective to thin, stack and wire bond. Cost can be 2X–4X price of flip chip ($200/wafer is the goal) and 5X–10X the price of wire bonding. TSV will be justified by performance, specifically an increase in inter-die I/O, increase in bandwidth, and a corresponding decrease in interconnect length. This paper will present two different approaches to the generation of TSVs as the vias can be created at various stages of the process: By the wafer provider, IC manufacturer, or packaging house. The paper will also address the techniques for creating the TSVs e.g. etching and lasering with respect to their differences and results as well as provide insight into the various approaches for filling the vias. A comparison between solid fill, polymer fill and no fill concepts will be made. Finally, the paper will address the three primary failure mechanisms for TSVs, that of, cracking of the copper plating, cracking of the silicon/change in resistance of silicon and interfacial delamination of the via wall from the silicon. The paper will conclude with a focus on the challenges for this technology as the exact process and architecture (materials, design) for TSV has yet to be finalized which in turn can lead to large changes in stress states.