VHDL-based FPGA Implementation of C/E System

Abstract

Petri Net is an important tool to model discrete event system. In this paper, Hardware Description Language VHDL is used to implement C/E System, a subclass of Petri Net. Firstly, C/E System is used to model the problem. The model is then analyzed and controlled. Secondly, Petri Net control model is described by VHDL and the VHDL source file is generated. Finally, the VHDL code is compiled, simulated, fit design and downloaded to the Programmable Logic Device FPGA through EDA software MAX PLUSII. Hardware experiment is performed with GW48-CK. A sample C/E System for the philosopher dining problem is presented in the paper using the proposed method. Simulation wave and hardware experiment further verify the correctness of the method. The VHDL-based FPGA implementation method is of great significance to the design of parallel controller based on C/E System.