Vertically Integrated Nanowires on Si Wafers and Into Circuits

Abstract

Vertically integrated copper (Cu) and nickel (Ni) nanowires (NWS) were fabricated on silicon using anodized aluminum oxide (AAO) thin film templates integrated onto silicon wafers. Both the AAO and NWs were mechanically robust and demonstrated to withstand further fabrication processes used for integrated circuits. The AAO pores were measured to be ~30 nm with size distributions narrowing from ±12 to ±6 nm after a second anodization. The NWs, therefore, had similar diameters and distributions inside these integrated AAO films. Magnetic hysteresis loops demonstrated the out-of-plane anisotropy of the vertically oriented Ni wires in the presence of pore outgrowth that had in-plane anisotropy. When used as vias and integrated with coplanar waveguides (CPWs), the Cu NWs had lower losses than standard vias above 60 GHz.