Abstract
In this letter, we present the fabrication and characteristics of a gate-all-around SONOS Flash memory using a vertical Si nanowire (SiNW), which is proposed to be the key building block to realize the 3-D multilevel memory technology for ultrahigh-density application. A highly scaled SiNW with a diameter down to 50 nm using CMOS-compatible technology was achieved. Using an unoptimized SONOS gate stack (with the thickness of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ~ 5/5/6 nm), the devices exhibit well-behaved memory characteristics, in terms of program/erase window, retention, and endurance properties.
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